MT42L256M32D4KP-3 IT:A【PDF 73/164 页】IC LPDDR2 SDRAM 8GBIT 168FBGA

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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4

PRECHARGE Command

Figure 52: WRITE Burst with Auto Precharge – WL = 1, BL = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

WL = 1

CA[9:0]

Bankn

col addr

Col addr

Bankn

row addr

Row addr

t WR

t RPpb

CMD

WRITE

NOP

NOP

NOP

NOP

NOP

NOP

ACTIVATE

NOP

DQS#

DQS

DQ

D IN A0

D IN A1

D IN A2

D IN A3

Transitioning data

Table 43: PRECHARGE and Auto Precharge Clarification

From

Command

READ

To Command

PRECHARGE to same bank as READ

Minimum Delay Between Commands

BL/2 + MAX(2, RU( t RTP/ t CK)) - 2

Unit

CLK

Notes

1

BST

PRECHARGE ALL

PRECHARGE to same bank as READ

PRECHARGE ALL

BL/2 + MAX(2,

1

1

RU( t RTP/ t CK))

-2

CLK

CLK

CLK

1

1

1

READ w/AP

PRECHARGE to same bank as READ w/AP

PRECHARGE ALL

BL/2 + MAX(2, RU( t RTP/ t CK)) - 2

BL/2 + MAX(2, RU( t RTP/ t CK)) - 2

CLK

CLK

1, 2

1

ACTIVATE to same bank as READ w/AP

BL/2 + MAX(2,

RU( t RTP/ t CK))

-2+

RU( t RPpb/

CLK

1

t CK)

WRITE or WRITE w/AP (same bank)

WRITE or WRITE w/AP (different bank)

READ or READ w/AP (same bank)

READ or READ w/AP (different bank)

Illegal

RL + BL/2 + RU( t DQSCKmax/ t CK) - WL + 1

Illegal

BL/2

CLK

CLK

CLK

CLK

3

3

3

3

WRITE

PRECHARGE to same bank as WRITE

WL + BL/2 +

RU( t WR/ t CK)

+1

CLK

1

PRECHARGE ALL

WL + BL/2 + RU( t WR/ t CK) + 1

CLK

1

BST

PRECHARGE to same bank as WRITE

PRECHARGE ALL

WL +

WL +

RU( t WR/ t CK)

RU( t WR/ t CK)

+1

+1

CLK

CLK

1

1

PDF: 09005aef83f3f2eb

2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN

73

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2010 Micron Technology, Inc. All rights reserved.

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MT42L256M32D4KP-MS 制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk